AMD’s Zen 4 architecture build on 5nm TSMC’s fabrication process may have a loaded package with various improvements to existing Zen cores. Well interpreted Zen 4 leaks occurred not long ago by famous Adored TV channel in YouTube. Previously, much anticipated DDR5 (Double Data Rate) memory and L2 Cache size increase were the main highlighted specs of Zen 4 architecture in order to eliminate major memory related bottlenecks that crippled some APUs and CPUs.
Fortunately, fresh leaks are suggesting that more changes will be brought to Zen 4 5nm architecture according to Tom from Moore’s Law Is Dead channel who’s having multiple sources with more accurate claims. Tom stressed on AMD’s aggressive stance on mobile laptop APUs generational improvements that might have a huge leap on performance improvements starting from Zen 4 release. About a core count strategy, AMD keeps tight-lipped on multi-core future plans and a specific source of Tom cannot confirm about doubling the core count in Zen 4 era.
Remember last year’s industrial leaks about AMD is up to something with it’s CPUs thread count? Exactly, SMT4 (Simultaneous Multi-Threading) feature may not come to Zen3 but it will be implemented for Zen 4 CPUs running on 5nm transistor shrink with matured strong architecture. It translates into 4 Threads Per Single Core feature that elevates overall performance up to 20-30%.
Large IPC (Instructions Per Cycle) increase is also seen on horizon by 10-15% uplift in performance since memory bottlenecks can finally be reduced significantly using DDR5 fast memory. Per SK Hynix claims, the DDR5 memory generation might run at 8400 Mhz effective speed which is a sweet dream of APU users. New AVX-512 instruction set is included for sure as previous leaks suggested.
Novel chipset design optimized for Zen 4 futuristic architecture is inbound to Ryzen 5000 processors’ performance tweaking. More importantly, X3D chip packaging solution will be implemented too because AMD strongly presented 3D stacked method to solve many previous unsolved latency issues at it’s Financial Analyst Day two months ago. Obviously, 3D packaging allows billions of transistors getting together stacked in three dimensional positions to achieve maximum efficiency and performance.
Larger Level 2 cache with a size of 1 MB instead of 512 KB is also supported by the latest leaks on Zen 4. Possibly, Level 4 cache appears to be featured in some Ryzen 5000 desktop CPU models but not all. Current PC industry still utilizes Level 3 Caching method so having DDR5 super fast memory in future generation CPUs you might want to think that L4 cache is necessary to complement each other.
Lastly, there will be a zero introduction on hardware level accelerators or co-processors unlike Intel. However, many new Zen 4 feature inventions by AMD ought to be incoming for Ryzen 5000 desktop CPUs instead of Ryzen 4000 series based on Zen 3 architecture. That’s it folks, thanks for reading fresh leaks information about 5nm Zen 4 microarchitecture potentially it would be incredible futuristic processors.
Source: Moore’s Law Is Dead via YouTube